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Features
* Sensor Keys: *
- Up to 11 QTouchTM channels Data Acquistion: - Measurement of keys triggered either by a signal applied to the SYNC pin or at regular intervals timed by the AT42QT1110's internal clock - Keys measured sequentially for better performance, or in parallel groups for faster operation - Raw data for key touches can be read as a report over the SPI interface Discrete Outputs: - Configurable "Detect" outputs indicating individual key touch (7-key mode) Device Setup: - Device configuration can be stored in EEPROM Technology: - Patented spread-spectrum charge-transfer (direct mode) Key Outline Sizes: - 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible, including solid or ring shapes Key Spacings: - 7 mm center to center or more (panel thickness dependent) Layers Required: - One Electrode Materials: - Etched copper, silver, carbon, Indium Tin Oxide (ITO) Electrode Substrates: - PCB, FPCB, plastic films, glass Panel Materials: - Plastic, glass, composites, painted surfaces (low particle density metallic paints possible) Panel Thickness: - Up to 10 mm glass, 5 mm plastic (electrode size dependent) Key Sensitivity: - Individually settable via simple commands over serial interface Adjacent Key Suppression(R) (AKSTM) - Patented AKS technology to enable accurate key detection Interface: - Full-duplex SPI slave mode (1.5 MHz), "change" pin, discrete detection outputs Moisture Tolerance Good Power: - 3V ~ 5.5V Package: - 32-pin 5 x 5 mm MLF RoHS compliant - 32-pin 7 x 7 mm TQFP RoHS compliant Signal Processing: - Self-calibration, auto drift compensation, noise filtering, AKS technology Applications: - Consumer and industrial applications, such as TV, media player, etc
* * * *
QTouchTM 11-key Sensor IC AT42QT1110-MU AT42QT1110-AU
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1. Pinout and Schematic
1.1 Pinout Configuration
SNS9K/DETECT5 SNS8K/DETECT3 SNS9/DETECT4 CHANGE RESET SNS10/DETECT6
SNS10K/SYNC
SNS0
SNS0K SNS1 SNS1K VDD VSS SNS2K SNS2 SNS3
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 QT1110 20 19 18 17 9 10 11 12 13 14 15 16
QT1110
SNS8/DETECT2 SNS7/DETECT1 SNS7K/DETECT0 VSS SNS6 SNS6K VDD SCK
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SNS5 SNS4K SNS4 SNS3K
MISO MOSI
SNS5K
SS
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1.2 Pin Descriptions
Pin Listing
Name SNS0K SNS1 SNS1K Vdd Vss SNS2K SNS2 SNS3 SNS3K SNS4 SNS4K SNS5 SNS5K SS MOSI MISO SCK Vdd SNS6K SNS6 Vss SNS7K/DETECT0 SNS7/DETECT1 SNS8/DETECT2 SNS8K/DETECT3 SNS9/DETECT4 SNS9K/DETECT5 CHANGE RESET SNS10/DETECT6 SNS10K/SYNC SNS0 Type I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/O I I O I P I/O I/O P I/O I/O I/O I/O I/O I/O OD I I/O I/O I/O Comments Sense Pin Sense Pin Sense Pin Power Supply Ground Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Enable SPI SPI Data In SPI Data Out SPI Clock Power Sense Pin Sense Pin Supply Ground Sense Pin/Key Status Indicator Sense Pin/Key Status Indicator Sense Pin / Key Status Indicator Sense Pin / Key Status Indicator Sense Pin / Key Status Indicator Sense Pin / Key Status Indicator Touch Event Indicator Reset Sense Pin / Key Status Indicator Sense Pin / Synchronization Input Sense Pin If Unused, Connect To... Leave open Leave open Leave open - - Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Vss via 100 k resistor to enable SPI Vdd via 100 k resistor to disable SPI Leave open Leave open Leave open - Leave open Leave open - Leave open Leave open Leave open Leave open Leave open Leave open Leave open Vdd Leave open Vdd or Vss via 100 k resistor Leave open
Table 1-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
I O
Input only Output only, push-pull
I/O OD
Input and output Open drain output
P
Ground or power 3
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1.3
Schematics
Typical Circuit: 7 keys With Detect Outputs and No External Trigger
Figure 1-1.
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Vunreg
VREG
QT1110
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Figure 1-2. Typical Circuit: 11 Keys With No External Trigger
Vunreg
VREG
QT1110
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Figure 1-3.
Typical Circuit: 10 Keys With External Trigger (SYNC Mode)
Vunreg
VREG
QT1110
Suggested voltage regulator manufacturers: * Torex (XC6215 series) * Seiko (S817 series) * BCDSemi (AP2121 series) Re Figure 1-1, Figure 1-2 and Figure 1-3 check the following sections for component values: * Section 3.1 on page 8: Cs capacitors (Cs0 - Cs10) * Section 3.2 on page 8: Sample resistors (Rs0 - Rs10) * Section 3.5 on page 9: Voltage levels * Section 3.3 on page 8: LED traces
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2. Overview of the AT42QT1110
2.1 Introduction
The AT42QT1110 (QT1110) is a digital burst mode charge-transfer (QTTM) capacitive sensor driver designed for any touch-key applications. The keys can be constructed in different shapes and sizes. Refer to the Touch Sensors Design Guide and Application Note QTAN0002, Secrets of a Successful QTouchTM Design, for more information on construction and design methods (both downloadable from the Atmel(R) website). The device includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. Only a few external parts are required for operation. The QT1110 modulates its bursts in a spread-spectrum fashion in order to suppress heavily the effects of external noise, and to suppress RF emissions.
2.2
Configurations
The QT1110 is designed as a versatile device, capable of various configurations. There are two basic configurations for the QT1110: * 11-key QTouch. The device can sense up to 11 keys. * 7-key QTouch with individual outputs for each key. The device can sense up to 7 keys and drive the matching Detect outputs to a user-configurable PWM. Both configurations allow for a choice of acquisition modes, thus providing a variety of possibilities that will satisfy most applications (see the following sections for more information). Additionally, the SYNC line can be used as an external trigger input. Note that in 11-key mode the SYNC line replaces one key, thus allowing only 10 keys. See Section 4.7 on page 18 for more information.
2.3
Guard Channel
The device has a guard channel option (available in all key modes), which allows one key to be configured as a guard channel to help prevent false detection. See Section 4.9 on page 19 for more information.
2.4
Self-test Functions
The QT1110 has two types of self-test functions: * Internal Hardware tests - check for hardware failures in the device's internal memory. * Functional checks - confirm that the device is operating within expected parameters. See Section 4.10 on page 20 for more information.
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3. Wiring and Parts
3.1 Cs Sample Capacitors
Cs0 - Cs10 are the charge sensing sample capacitors. Normally they are identical in nominal value. The optimal Cs values depend on the thickness of the panel and its dielectric constant. Thicker panels require larger values of Cs. Values can be in the range 2.2 nF (for faster operation) to 33 nF (for best sensitivity); typical values are 4.7 nF to 10 nF. The value of Cs should be chosen so that a light touch on a key produces a reduction of ~20 to 30 in the key signal value (see Section 6.8 on page 26). The chosen Cs value should never be so large that the key signals exceed ~1000, as reported by the chip in the debug data. The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they should have a 10 percent tolerance. Twenty percent tolerance may cause small differences in sensitivity from key to key and unit to unit. If a key is not used, the Cs capacitor may be omitted.
3.2
Rs Resistors
The series resistors Rs0 - Rs10 are inline with the electrode connections and should be used to limit electrostatic discharge (ESD) currents and to suppress radio frequency (RF) interference. Values should be approximately 2 kto 20 k each; a typical value is 4.7 k. Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency interference (RFI). For details of how to select these resistors see the Application Note QTAN0002, Secrets of a Successful QTouchTM Design, downloadable from the Touch Technology area of Atmel's website, www.atmel.com.
3.3
LED Traces and Other Switching Signals
Digital switching signals near the sense lines can induce transients into the acquired signals, deteriorating the SNR performance of the device. Such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). LED terminals which are multiplexed or switched into a floating state, and which are within, or physically very near, a key (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 1 nF capacitor. This is to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type. LED terminals which are constantly connected to Vss or Vdd do not need further bypassing.
3.4
PCB Cleanliness
Modern no-clean flux is generally compatible with capacitive sensing circuits. CAUTION: If a PCB is reworked to correct soldering faults relating to the QT1110, or to any associated traces or components, be sure that you fully understand the nature of the flux used during the rework process. Leakage currents from hygroscopic ionic residues can stop capacitive sensors from functioning. If you have any doubts, a thorough cleaning after rework may be the only safe option.
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3.5
3.5.1
Power Supply
General Considerations See Section 8.2 on page 38 for the power supply range. If the power supply fluctuates slowly with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. The usual power supply considerations with QT parts apply to the device. The power should be clean and come from a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and, except in extreme conditions, should not require a separate Low Dropout (LDO) regulator. See underneath Figure 1.3 on page 4 for suggested regulator manufacturers. Caution: A regulator IC shared with other logic can result in erratic operation and is not advised. A single ceramic 0.1 F bypass capacitor, with short traces, should be placed very close to the power pins of the IC. Failure to do so can result in device oscillation, high current consumption, erratic operation etc. It is assumed that a larger bypass capacitor (like1 F) is somewhere else in the power circuit; for example, near the regulator.
3.5.2
Brownout Detection The QT1110 includes a power supply monitoring circuit that detects if Vdd drops below a safe operating voltage. When this occurs, the device goes into a "Reset" state, where no acquisition or processing is carried out. The device remains in this state until Vdd returns to the specified voltage range. Once a safe operating voltage is detected, the QT1110 behaves as per normal power-on/reset conditions; that is, any saved settings are restored from EEPROM, the internal self-tests are run and all channels are calibrated. The Brown-out detector threshold is 2.7V 10 percent.
3.6
MLF Package Restrictions
The central pad on the underside of the MLF chip should be connected to ground. Do not run any tracks underneath the body of the chip, only ground. Figure 3-1 shows an example of good/bad tracking. Figure 3-1. Examples of Good and Bad Tracking
Example of GOOD Tracking
Example of BAD Tracking
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4. Detailed Operations
4.1
4.1.1
Communications
Introduction All communication with the device is carried out over the Serial Peripheral Interface (SPI). This is a synchronous serial data link that operates in full-duplex mode. The host communicates with the QT controller over the SPI using a master-slave relationship, with the QT1110 acting in slave mode.
4.1.2
SPI Operation The SPI uses four logic signals: * Serial Clock (SCK) - output from the host. * Master Output, Slave Input (MOSI) - output from the host, input to the QT controller. Used by the host to send data to the QT controller. * Master Input, Slave Output (MISO) - input to the host, output from the QT controller. Used by the QT device to send data to the host. * Slave Select (SS) - active low output from the host. At each byte, the master pulls SS low and generates 8 clock pulses on SCK. With these 8 clock pulses, a byte of data is transmitted from the master to the slave over MOSI, most significant bit (msb) first. Simultaneously a byte of data is transmitted from the slave to the master over MISO, also most significant bit first. The slave reads the status of MOSI at the leading edge of each clock pulse, and the master reads the slave's data from MISO at the trailing edge. The QT1110 requires that the clock idles "high", meaning that the data on MOSI and MISO pins are set at the falling edges and sampled at the rising edges. That is: Clock polarity CPOL = 1 Clock phase CPHA = 1 The QT1110 SPI interface can operate at any SCK frequency up to 1.5 MHz. In multibyte communications, the master must pause for a minimum delay of 150 s between the completion of one byte exchange and the beginning of the next. Note that the number of bytes to be transmitted depends on the initial command sent by the host. This sets the mode on the QT1110 so that the QT1110 knows how to respond to, or how to interpret, the following bytes. If there is a delay of >100 ms between bytes while the QT1110 is waiting for data, or waiting to send data, then the incomplete transmission is discarded and the device resets its SPI state machine. It will then interpret the next byte it receives as a fresh command. When the QT1110 SPI interface is receiving a new command, it returns the "Idle" status code (0x55) on MISO during the first byte exchange to indicate to the master that it is in the correct state for receiving instructions.
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4.1.3 CRC Bytes If enabled, a CRC checking procedure is implemented on all communications between the SPI master and the QT1110. In this case, each command or report request sent by the master must have a byte appended containing the CRC checksum of the data sent. The QT1110 will not respond to commands until the CRC byte has been received and verified. Sample C code showing the algorithm for calculating the CRC of the data can be found in Appendix A. When the QT1110 is expecting a CRC byte, it returns (on MISO) the calculated CRC byte which it expects to receive. This is sent simultaneously with the QT1110 receiving the CRC byte from the master (that is, during the same byte exchange). This allows both devices to confirm that the data was sent correctly. All data returned by the QT1110 is also be followed by a CRC byte, allowing the master to confirm the integrity of the data transmission. 4.1.4 SPI Commands There are three types of communication between the SPI master and the QT1110: * Control commands (see Section 5 on page 22) - To send control instructions to the QT1110 * Report requests (see Section 6 on page 24) - To reading status information from the QT1110 * Setup commands (see Section 7 on page 28) - To set configuration options ("Set" instructions) - To read configuration options ("Get" instructions) Additionally the "Null" command (0x00) is transmitted by the host device as it is receiving data from the QT1110. 4.1.4.1 Control Commands A control command is an instruction sent to the QT1110 that controls operations of the device, and for which no response is required. Examples of control commands are: "Reset", "Calibrate", "Send Setups". With the exception of "Send Setups", control commands normally require a single byte exchange, unless CRC checking is enabled, in which case a second byte must be transmitted by the host with the calculated CRC of the command byte. Figure 4-1. Sleep Command - CRC Disabled
Host (Sends on MOSI)
Command: 0x05
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
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Figure 4-2.
Sleep Command - CRC Enabled
Host (Sends on MOSI)
Command: 0x05
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
Command CRC: 0x3F Response: 0x3F (Expected Command CRC)
When the "Send Setups" command is received, the QT1110 stops measurement of QTouch sensors and waits for 42 bytes of data to be sent. Only when all 42 bytes have been received (and the CRC byte, if CRC is enabled), the QT1110 applies all the settings to RAM and resumes measurement. In this case, if CRC is enabled, the CRC byte is calculated for all the data sent by the host, including the command byte 0x01. Control Commands are specified in detail in Section 5 on page 22. 4.1.5 Report Requests Report Requests are sent by the Host to instruct the QT1110 to return status information. The host sends the appropiate "Report Request" command, then transmits Null bytes on MOSI while the QT1110 returns the report data on MISO. Figure 4-3. All Keys Report - CRC Disabled
Host (Sends on MOSI)
Command: 0xC1
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
Null: 0x00 Key Status Report Byte 0
Null: 0x00 Key Status Report Byte 1
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For example, Figure 4-3 on page 12 shows the exchange that takes place to read the 2-byte "All Keys" report. In this exchange, the host sends: 0xC1 -- 0x00 -- 0x00 and the QT1110 returns (simultaneously): 0x55 -- Report Byte 0 -- Report Byte 1 If CRC is enabled, this exchange is extended to 5 bytes, as shown in Figure 4-4. Figure 4-4. All Keys Report - CRC Enabled
Host (Sends on MOSI)
Command: 0xC1
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
Command CRC: 0x94 Response: 0x94 (Expected Command CRC)
Null: 0x00 Key Status Report Byte 0
Null: 0x00 Key Status Report Byte 1
Null: 0x00 Report CRC: 0x??
4.1.5.1
Set Instructions Set Instructions are 2-byte transmissions by the host that are used to send settings to individual locations in the device memory map. At the first byte, the QT1110 returns 0x55 ("Idle") to confirm that it will interpret the byte as a new command. At the second byte, the QT1110 returns the "Set" command it has just received. For example, to set the "Positive Recalibration Delay" to 1920 ms, address 5 in the memory map is set to 12 (0x0C). This is done with the "Set" command for address 5 (command code 0x95), as shown in Figure 4-5 on page 14.
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Figure 4-5.
Positive Recalibration Delay Set Instruction - CRC Disabled
Host (Sends on MOSI)
Command: 0x95
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
"Set" Data: 0x0C Response: 0x95 (Command Just Received)
With CRC Enabled, a CRC byte is also required (Figure 4-6). This is calculated for the two transmitted bytes (that is, the "Set" command and the data byte). For example, for the sequence shown in Figure 4-5 (0x95 -- 0x0C), the CRC Byte is 0x9F. As is the case with the other command types, when the QT1110 is expecting a CRC byte from the host, it calculates that byte in advance and returns the expected value to the host in the same transmission as the host sends the CRC byte. The sent data is not applied to the memory location until the CRC byte has been received and verified. Figure 4-6. Positive Recalibration Delay Set Instruction - CRC Enabled
Host (Sends on MOSI)
Command: 0x95
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
"Set" Data: 0x0C Response: 0x95 (Command Just Received)
Command CRC: 0x9F Response: 0x9F (Expected CRC)
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4.1.5.2 Get Instructions Get instructions are instructions that read the data from a location in the QT1110 memory map. Figure 4-7. Positive Recalibration Delay Get Instruction - CRC Disabled
Host (Sends on MOSI)
Command: 0xD5
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
Null: 0x00 "Get" Data: 0x0C (Positive Recalibration Delay)
The host sends the appropriate "Get" command, followed by a "Null" byte. The QT1110 returns the contents of the addressed memory location. Figure 4-7 on page 15 shows the exchange for a report on the positive recalibration delay (assuming that the data byte is 0x0C). With CRC Enabled, this exchange takes 4 bytes, with a command CRC transmitted by the host and a report CRC returned by the QT1110 (see Figure 4-8). Figure 4-8. Positive Recalibration Delay Get Instruction - CRC Enabled
Host (Sends on MOSI)
Command: 0xD5
Device (Responds on MISO)
Response: 0x55 ("Idle" - Fresh Command)
Simultaneous Transmission
Command CRC: 0x68 Response: 0x68 (Expected Command CRC)
Null: 0x00 "Get" Data: 0x0C (Positive Recalibration Delay)
Null: 0x00 "Get" CRC: 0xA3
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4.1.6 4.1.6.1
Quick SPI Mode Introduction In Quick SPI Mode, the QT1110 sends a 7-byte key report at each exchange. No host commands are required over SPI in this mode; the host clocks the data bytes out in sequence.
4.1.6.2
Quick SPI Report The 7 report bytes are in the format given in Table 4-1. Table 4-1.
Byte 0 1 2 3 4 5 6
Device Status Report Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Counter - increments from 0 to 255 Channel 3 Channel 7 Reserved Channel 3 Channel 7 Reserved Channel 2 Channel 6 Channel 10 Channel 2 Channel 6 Channel 10 Channel 1 Channel 5 Channel 9 Channel 1 Channel 5 Channel 9 Channel 0 Channel 4 Channel 8 Channel 0 Channel 4 Channel 8
Description Counter Detect status, channels 0 - 3 Detect status, channels 4 - 7 Detect status, channels 8 - 10 Error status, channels 0 - 3 Error status, channels 4 - 7 Error status, channels 8 - 10
where: * Byte 0 is a counter that increments from 0 to 254 on successive exchanges to confirm that firmware is operating correctly. * Bytes 1 - 3 indicate the detect status of channels 0 - 3, 4 - 7 and 8 - 10 respectively (two bits per channel), as follows: - 00 = Channel not in detect - 01 = Channel in detect - 10 = Not Allowed - 11 = Invalid Signal (Channel disabled) * Bytes 4 - 6 indicate the error status of channels 0 - 3, 4 - 7 and 8 - 10 respectively (two bits per channel), as follows: - 00 = No error - 01 = Not allowed - 10 = Error on channel - 11 = Invalid signal (channel disabled) 4.1.6.3 Commands in Quick SPI Mode Only two host commands are recognized under Quick SPI mode. These are shown in Table 4-2. Table 4-2.
Command Store to EEPROM Enable Full SPI
Host Commands in Quick SPI Mode
Code 0x0A 0x36 Purpose Allows for "Quick SPI mode" to be stored as the default start-up mode Enables full SPI mode
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4.1.6.4 Quick SPI Mode timing In Quick SPI mode, the minimum time between byte exchanges is reduced to 50 S. If a pause in communications of 100 ms is detected during reading of the 7-byte report, the QT1110 resets the exchange, and on the next byte read it returns byte 0 of the report.
4.2
Reset
The QT1110 can be reset using one of two methods: * Hardware reset: An external reset logic line can be used if desired, fed into the RESET pin. However, under most conditions it is acceptable to tie RESET to Vdd. * Software reset: A software reset can be forced using the "Reset" control command. For both methods, the device will follow the same initialization sequence. If there any saved settings in the EEPROM, these are loaded into RAM. Otherwise the default settings are applied. Note: The SPI interface becomes active after the QT1110 has completed its startup sequence, taking approximately 160 ms after power on/reset.
4.3
Sleep Mode
The QT1110 can be put into a very low power sleep mode (typically < 2 A). During sleep mode, no keys are measured and the DETECT outputs are all put into high impedience mode to minimize current consumption. The device remains in sleep mode until a falling edge is detected on either the SS pin or the CHANGE pin. When the QT1110 wakes from sleep mode, it continues to operate as it was before it was put into sleep mode. The QT1110 requires approximately 100 s to wake from sleep mode and will not respond correctly to SPI communications until the wake-up procedure is complete. The low level on the SS or CHANGE pin that is used to wake the device must be maintained for 100 s to ensure correct operation. Note: If the device is set to sleep mode for an extended period, the host should initiate a recalibration immediately after waking the QT1110.
4.4
Calibration
The device can be forced to recalibrate the sensor keys at any time. This can be useful where, for example, a portable device is plugged into mains power, or during product development when settings are being tuned. The QT1110 can also be configured to automatically recalibrate if it remains in detection for too long. This avoids keys becoming "stuck" after a prolonged period of uninterrupted detection. See Section 7.18 on page 37 for details.
4.5
CHANGE Pin
The CHANGE pin can be configured using the Comms Options setup byte (see Section 7.5 on page 30) to act in one of two modes: * Data mode - The CHANGE pin is asserted (pulled low) when the detection status of a key changes from that last sent to the host; that is when a key-touch or key-release event occurs. - The CHANGE pin is pulled low when a key's status changes and is only released when the "Send All keys" report is requested (0xC1), or the key status information bytes are read in Quick SPI mode (see Section 7.5 on page 30).
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* Touch mode - The CHANGE pin is pulled low when one or more keys are in detect. The CHANGE pin remains low as long as there is a key in detect, regardless of communications. - The CHANGE pin is released when there are no keys in detect. No host communications are required to release the CHANGE pin.
4.6
Stand-alone Mode
The QT1110 can operate in a stand-alone mode without the use of the SPI interface. The settings are loaded from EEPROM and the device operates in 7-key mode using the Detect outputs.
4.7
4.7.1
Key Modes
11-key Mode In 11-key mode, the device can sense up to 11 keys. Alternatively, one key can be replaced by the SYNC line as an external trigger input (see Section 4.8.2 on page 19). 11-key mode is configured by setting the "MODE" bit in the Device Mode setup byte (see Section 7.4 on page 29). Key acquisition can be triggered in one of two ways: using the internal clock to trigger acquisition either at a fixed repetition period or in a continuous "free run" mode (see Section 4.8.1), or using the SYNC pin to provide an external trigger (see Section 4.8.2 on page 19),
4.7.2
7-key Mode In 7-key mode, the detect outputs DETECT0 to DETECT6 become active on pins 22-27 and 30. These outputs provide configurable PWM signals that indicate when each of the keys is touched. 7-key mode is configured by clearing the "MODE" bit in the Device Mode setup byte (see Section 7.4 on page 29). Each DETECT output can be individually configured to output a PWM signal while the matching key is in detect or out of detect. This signal can be one of nine levels, ranging from low (PWM = 0 percent) to high (PWM = 100 percent). This allows for the use of an indicating LED. This is achieved by enabling the appropriate bit in the Key to LED setup byte (see Section 7.14 on page 35), and setting the desired outputs levels or PWMs in setup addresses 9 to 15 (see Section 7.12 on page 33).
4.8
4.8.1
Trigger Modes
Timed Trigger In 11-key mode, The QT1110 can be configured to use the internal clock as a timed trigger. In this case, the QT1110 is configured with a cycle period, such that each acquisition cycle starts a specified length of time after the start of the previous cycle. If the cycle period is set to "0", each acquisition cycle starts as soon as the previous one has finished, resulting in the acquisition cycles running back-to-back in a "free run" mode. The use of a timed trigger, and the cycle period to be used, is set in the Device Mode setup byte (see Section 7.4 on page 29).
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4.8.2 Synchronized Trigger In 11-key mode, if a time trigger is not enabled, the QT1110 operates in "synchronized" mode. In this mode, SNS10K is used as a SYNC pin to trigger key acquisition, rather than using the device's internal clock. In this case the maximum number of keys is reduced to 10. The SYNC pin can use one of two methods to trigger key measurements, selectable via bit 4 of the Device Mode setup byte (see Section 7.4 on page 29): Low Level and Rising Edge. With the Low Level method the QT1110 operates in "free run" mode for as long as the SYNC pin is read as a logical "0". When the SYNC pin goes high, the current measurement cycle will be finished and no more key measurements will be taken until the SYNC pin goes low again. The low level trigger should be a minimum of 1 ms so that there is sufficient time for the device to detect the low level. With the Rising Edge method all enabled keys are measured once when a rising edge is detected on the SYNC pin. This allows key measurements to be synchronized to an external event or condition. For example, the SYNC pin can be used by the host to synchronize several devices to each other. This would ensure that only one of the devices outputs pulses at any given time and signals from one QT1110 do not interfere with the measurements from another. Another use for synchronizing to the rising edge is to steady the signals when the device is running off a mains transformer with insufficient mains frequency filtering that is causing a 50Hz or 60Hz ripple on Vdd. If the mains voltage is scaled down with a simple voltage divider and connected to the SYNC pin, then the key measurement can be triggered by the rising edge detected at a positive going zero-crossing. Note that in this case, each key signal will be taken at the same point in the cycle, so Vdd will be the same at each measurement for a given key and the signals will be steadier.
4.9
Guard Channel Option
The device has a guard channel option (available in all key modes), which allows one key to be configured as a guard channel to help prevent false detection (see Figure 4-9 on page 20). Guard channel keys should be more sensitive than the other keys (physically bigger or larger Cs), subject to burst length limitations (see Section 4.11.2 on page 21). With guard channel enabled, the designated key is connected to a sensor pad which detects the presence of touch and overrides any output from the other keys using the chip's AKS feature. The guard channel option is enabled by the Guard Key setup byte (see Section 7.5 on page 30). With the guard channel not enabled, all the keys work normally. Note: If a key is already "in detect" when the guard channel becomes active, that key will remain in detect and the guard key will not activate until the active key goes out of detect.
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Figure 4-9.
Guard Channel Example
Key Pad Formed of Six Keys
Guard Channel Formed of One Key
4.10
4.10.1
Self-test Functions
Internal Hardware Tests Internal hardware tests check for hardware failure in the device's internal memory areas and data paths. Any failure detected in the function or contents of application ROM, RAM or registers causes the device to reset itself. The application code is scanned with a CRC check routine to confirm that the application data is all correct. The RAM and registers are checked periodically (every 10 seconds) for dynamic and static failures.
4.10.2
Functional Checks Functional checks confirm that the device is operating within expected parameters; any failure detected in these tests is notified to the system host. The device will continue to operate in the event that such functional failures are detected. The functional tests are: * Check that the channel-measurement signals are within the defined range. * Confirm that data stored in the EEPROM is valid. These tests are carried out as the particular functions are used. For example, the EEPROM is checked when the device attempts to load data from EEPROM, and the channel signals are checked when a measurement is carried out. Note: If a particular channel is unused, the threshold of that channel should be set to 0 to prevent the incorrect reporting of the unused channel as being in an error state.
4.11
4.11.1
Signal Processing
Detection Integrator The device features a detection integration mechanism, which acts to confirm a detection in a robust fashion. A per-key counter is incremented each time the key has exceeded its threshold. When this counter reaches a preset limit the key is finally declared to be touched. For example, if the DI limit is set to 10, then a key's signal must fall by more than the key threshold, and remain below that level for 10 acquisitions, before the key is declared to be touched. Similarly, the DI is applied to a key that is going out of detect: it must take 10 acquisitions where the signal has not exceeded its detect threshold before it is declared to leave touch.
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4.11.2 Burst Length Limitations The maximum burst length is 2048 pulses. The recommended design is to use a capacitor that gives a signal of <1000 pulses. The number of pulses in the burst can be obtained by reading the key signal (that is, the number of pulses to complete measurement of the key's signal) over the SPI interface (see Section 6.8 on page 26). Alternatively, a scope can be used to measure the entire burst, and then the burst length divided by the time for a single pulse. Note that the keys are independent of each other. It is therefore possible, for example, to have a signal of 100 on one key and a signal of 1000 on another. 4.11.3 Adjacent Key Suppression Technology The device includes Atmel's patented Adjacent Key Suppression (AKS) technology to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. AKS is enabled or disabled for each key individually; only one key out of those enabled for AKS may be reported as touched at any one time. The first key touched dominates and stays in detect until it is released, even if another stronger key is reported. Once it is released, the next strongest key is reported. If two keys are simultaneously detected, the strongest key is reported, allowing a user to slide a finger across multiple keys with only the dominant key reporting touch. Each key can be enabled for AKS processing via the AKS mask (see Section 7.11 on page 33). Keys outside the group of enabled keys may be in detect simultaneously.
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5. Control Commands
5.1 Introduction
The QT1110 control commands are those commands that affect the device operation. The control commands are listed in Table 5-1 and are described individually in the following sections. Table 5-1.
Command Send Setups Calibrate All Reset Sleep Store to EEPROM Restore from EEPROM Erase EEPROM Recover EEPROM Calibrate Key 'k'
Control Commands
Code 0x01 0x03 0x04 0x05 0x0A 0x0B 0x0C 0x0D 0x1k Note Configures the device to receive setup data Calibrates all keys Resets the device Sleep (dead) mode Stores RAM setups to EEPROM Copies EEPROM setups to RAM (automatically done at startup) Erases EEPROM setups Restores last EEPROM settings (after erase) Calibrates one key (key k)
Note:
Commands are implemented immediately upon reception, so a suitable delay is required for the operation to be completed before communications can be re-established.
5.2
Send Setups (0x01)
This command initiates the upload of the full settings table to the QT1110 (see Section 7 on page 28). When this command is received, the QT1110 stops key measurement and waits until 42 bytes of setup data have been received. Key acquisition will restart after all the setup data has been received. If enabled, a CRC check byte is transmitted (both ways) after the 42 bytes to confirm that they have been received correctly. If CRC checking is not enabled, it is recommended that the host request a dump of setup data from the QT1110, and confirms that the data correctly matches the data sent. The host must wait for at least 150 s for the operation to be completed before communications can be re-established.
5.3
Calibrate All (0x03)
This command initiates the recalibration of all sensor keys. The host must wait for at least 150 s for the operation to be completed before communications can be re-established.
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5.4 Reset (0x04)
The Reset command forces the QT1110 to reset. If the setups data is present in the EEPROM, the setups are loaded into the device. Otherwise default settings are applied. The host must wait for at least 160 ms for the operation to be completed before communications can be re-established.
5.5
Sleep (0x05)
The Sleep command puts the device into sleep mode (see Section 4.3 on page 17). The host must wait for at least 150 s after a low signal is applied to the SS or CHANGE pin to wake the device before communications can be re-established.
5.6
Store to EEPROM (0x0A)
Stores the current RAM contents to the QT1110's internal EEPROM. When the device is reset, it will automatically reload these settings. The host must wait for at least 200 ms for the operation to be completed before communications can be re-established.
5.7
Restore from EEPROM (0x0B)
Settings stored in EEPROM are automatically loaded into RAM when the device is reset. If desired, these settings can be re-loaded into RAM using the `Restore from EEPROM' command. The host must wait for at least 150 ms for the operation to be completed before communications can be re-established.
5.8
Erase EEPROM (0x0C)
This command erases the settings stored in EEPROM and then resets the QT1110. This causes the QT1110 to revert to its default settings. The host must wait for at least 50 ms for the operation to be completed before communications can be re-established.
5.9
Recover EEPROM (0x0D)
This command "undeletes" the setup data that was previously stored in the device's EEPROM and has been erased using the "Erase EEPROM" command. Note: If valid settings have not previously been stored in the device EEPROM, the QT1110 continues to operate under the default settings.
The host must wait for at least 50 ms for the operation to be completed before communications can be re-established.
5.10
Calibrate Key (0x1k)
This command recalibrates the key specified by "k". For example, to calibrate key 4, the host sends "0x14"; to calibrate key 10, the host sends "0x1A". The host must wait for at least 150 s for the operation to be completed before communications can be re-established.
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6. Report Requests
6.1 Introduction
The host can request reports from the QT1110, as summarized in Table 6-1. Table 6-1.
Command Send First Key Send All keys Device Status EEPROM CRC RAM CRC Error Keys Signal for Key "k"' Reference for Key "k" Status for Key "k" Detect Output States Last Command Setups Device ID Firmware Version
Report Requests
Code 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0x2k 0x4k 0x8k 0xC6 0xC7 0xC8 0xC9 0xCA Note Returns the first detected key Returns all keys Returns the device status Returns the EEPROM CRC Returns the RAM CRC Returns the error keys Returns the signal for key "k" Returns the reference for key "k" Returns error conditions/touch indication Returns the detect output states Returns the last command sent to QT1110 Returns the setup data Returns the device ID Returns the firmware version Data Returned 1 byte 2-byte bitfield 1-byte bitfield 1 byte 1 byte 2-byte bitfield 2-byte number 2-byte number 1 byte 1 byte 1 byte 42 bytes 1 byte 1 byte
Note that SPI communications are full-duplex, so the host must transmit on the MOSI pin to keep the communications active, while reading data from the QT1110 on the MOSI pin. Failure to do this within 100 ms will cause the device to assume that the exchange has been abandoned and reset the SPI interface. The host should therefore send one or two "NULL" bytes, as appropriate, on the MOSI line as it receives the 1- or 2-byte report data from the device.
6.2
First Key (0xC0)
This command returns 1-byte report in the format shown in Table 6-2. Table 6-2. Send First Key Report Format
Bit 7 Byte 0 DETECT Bit 6 NUMKEY Bit 5 ERROR Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
KEY_NUM
DETECT: 0 = no key in detect; 1 = there is a key in detect. NUMKEY: indicates the number of keys in detect: 0 = only one key is in detect (specified by "KEY_NUM") 1 = more than one key in detect. ERROR: 0 = there are no keys in an error state; 1 = at least one key is in error state. KEY_NUM: the key number (0 to 10) of the key in detect (if there is only one), or the number of the first key to go into detection when there are more than one. 24
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6.3 All Keys (0xC1)
Returns a 2-byte bit-field report indicating the detection status of all 11 keys. Table 6-3. Send All Keys Report Format
Bit 7 Byte 0 Byte 1 KEY_7 KEY_6 KEY_5 KEY_4 KEY_3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 KEY_10 KEY_2 Bit 1 KEY_9 KEY_1 Bit 0 KEY_8 KEY_0
KEY_n: 0 = key n out of detect, 1 = key n in detect (where n is 0-10).
6.4
Device Status (0xC2)
This command returns a 1-byte bit-field report indicating the overall status of the QT1110. Table 6-4.
Byte 0
Device Status Report Format
Bit 7 1 Bit 6 DETECT Bit 5 CYCLE Bit 4 ERROR Bit 3 CHANGE Bit 2 EEPROM Bit 1 RESET Bit 0 GUARD
Bits 7 is always 1; the other bits are as follows: DETECT: 0 = no key in detect, 1 = at least 1 key in detect. CYCLE: 0 = cycle time is good, 1 = cycle time over-run. A cycle time over-run occurs when it takes longer to measure and process all the keys than the assigned cycle time. ERROR: 0 = no key in error state, 1 = at least 1 key in error. CHANGE: 0 = CHANGE pin is asserted, 1 = CHANGE pin is floating. EEPROM: 0 = EEPROM is good, 1 = EEPROM has an error. If there are no settings stored in EEPROM, the EEPROM error bit is set and a zero EEPROM CRC is returned. RESET: set to 1 after power-on or reset, cleared when "Device Status" is read. GUARD: 0 = guard channel is not in detect, 1 = guard channel is active or in detect. This bit will be zero if the guard channel is not enabled.
6.5
EEPROM CRC (0xC3)
This command returns a 1-byte CRC checksum for the setup data in EEPROM.
6.6
RAM CRC (0xC4)
This command returns a 1-byte CRC checksum for the setup data in RAM.
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6.7
Error Keys (0xC5)
This command returns a 2-byte bit-field report indicating the error status of all 11 keys. Note that disabled keys do not report errors. Table 6-5.
Byte 0 Byte 1 KEY_7 KEY_6 KEY_5 KEY_4 KEY_3
Send All Keys Report Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 KEY_10 KEY_2 Bit 1 KEY_9 KEY_1 Bit 0 KEY_8 KEY_0
KEY_n: 0 = key n status good, 1 = key n in error (where n is 0-10).
6.8
Signal for Key "k" (0x2k)
This command returns a 2-byte report containing the most recent measured signal for key "k". The signal is returned as a 16-bit number, MSB first. Table 6-6.
Byte 0 Byte 1
Signal for Key "k" Report Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Signal MSB Signal LSB
6.9
Reference for Key "k" (0x4k)
This command returns a 2-byte report containing the reference signal for key "k". The reference is returned as a 16-bit number, MSB first. Table 6-7.
Byte 0 Byte 1
Reference for Key "k" Report Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference MSB Reference LSB
6.10
Status for Key "k" (0x8k)
This command returns a 1-byte report containing the status for key "k". Table 6-8.
Byte 0
Reference for Key "k" Report Format
Bit 7 DETECT Bit 6 LBL Bit 5 MBL Bit 4 Bit 3 Bit 2 AKS_EN Bit 1 CAL Bit 0 KEY_EN
DETECT: 0ut of detect, 1 = in detect. LBL: 0 = lower burst limit is good, 1 = lower burst limit has error. MBL: 0 = maximum burst limit is good, 1 = maximum burst limit has error. The maximum burst limit is fixed at 2048 pulses. AKS_EN: 0 = AKS is disabled, 1 = AKS is enabled. CAL: 0 = normal, 1 = calibrating. KEY_EN: 0 = key is disabled, 1 = key is enabled.
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6.11 Detect Output States (0xC6)
This command returns a byte that indicates which PWM signal is applied to each DETECT pin. Table 6-9. Reference for Key "k" Report Format
Bit 7 Byte 0 Bit 6 DET_6 Bit 5 DET_5 Bit 4 DET_4 Bit 3 DET_3 Bit 2 DET_2 Bit 1 DET_1 Bit 0 DET_0
DET_n: 0 = "Out of Detect" PWM is output, 1 = the "In Detect" PWM is output. Note: Note: During "LED Detect Hold Time" or "LED Fade", the report indicates the new state of the DETECT pin. For example, if the DETECT output is in "LED Detect Hold Time" before switching to "Out of Detect" PWM, the reported state is "0".
6.12
Last Command (0xC7)
This command returns the previous 1-byte command that was received from the host. Note that this command does not return itself. Table 6-10.
Byte 0
Reference for Key "k" Report Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Last Command
6.13
Setups (0xC8)
This command returns the 42 bytes of the setups table, starting with address 0, with the most significant bit first.
6.14
Device ID (0xC9)
This command returns 1 byte containing the device ID (0x57). Table 6-11. Device ID Report Format
Bit 7 Byte 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Device ID = 0x57
6.15
Firmware Version (0xCA)
Returns 1 byte containing the firmware version. Table 6-12.
Byte 0
Firmware Version Report Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Major Version Minor Version
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7. Setups and Status Information
7.1 Introduction
The bytes of the setup table can be written to or read from individually. The setup table and the corresponding "Set" and "Get" commands are listed in Table 7-1. Note that there is a discontinuity in the "Set" and "Get" commands; 0xAF and 0xEF are not implemented. Table 7-1.
Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Memory Map
Function Device Mode Guard Key/Comms Options Detect Integrator (DI)/Drift Hold Time (DHT) Positive Threshold (PTHR)/Positive Hysterisis (PHYST) Positive Drift Compensation (PDRIFT) Positive Recalibration Delay (PRD) Lower Burst Limit (LBL) AKS Mask: Keys 8-10 AKS Mask: Keys 0-7 Detect0 PWM "Detect"/PWM "No Detect" Detect1 PWM "Detect"/PWM "No Detect" Detect2 PWM "Detect"/PWM "No Detect" Detect3 PWM "Detect"/PWM "No Detect" Detect4 PWM "Detect"/PWM "No Detect" Detect5 PWM "Detect"/PWM "No Detect" Detect6 PWM "Detect"/PWM "No Detect" LED Detect Hold Time LED Fade/Key to LED LED Latch Key0 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key1 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key2 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key3 Negative Threshold (NTHR /Negative Hysterisis (NHYST) Key4 Negative Threshold (NTHR /Negative Hysterisis (NHYST) Key5 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key6 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key7 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key8 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key9 Negative Threshold (NTHR)/Negative Hysterisis (NHYST) Key10 NegativeThreshold (NTHR)/Negative Hysterisis (NHYST) Extend Pulse Time Key0 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Set Command 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xB0 Get Command 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xF0
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Table 7-1.
Address 32 33 34 35 36 37 38 39 40 41
Memory Map (Continued)
Function Key1 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key2 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key3 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key4 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key5 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key6 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key7 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key8 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key9 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Key10 Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD) Set Command 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA Get Command 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA
7.2
Setting Individual Settings
To set up an individual setup value, the host sends the command listed under the "Set Command" column in Table 7-1, followed by a byte of data. For details of the communication flow, see Section 4.1 on page 10.
7.3
Setting All the Setups
The host can send all 42 bytes of setup data to the QT1110 as a block using the Send Setups command. See Section 5.2 on page 22 for details.
7.4
Address 0: Device Mode
The Device Mode controls the overall operation of the device: number of keys, acquisition method, timing and trigger mechanism. Table 7-2.
Address 0
Device Mode
Bit 7 KEY_AC Bit 6 MODE Bit 5 SIGNAL Bit 4 SYNC Bit 3 Bit 2 Bit 1 Bit 0
REPEAT_TIME
KEY_AC: selects the trigger source to start key acquisition; 0 = SYNC pin, 1 = timed. MODE: selects 7-key or 11-key mode; 0 = default 7-key mode, 1 = 11-key mode. SIGNAL: selects serial or parallel acquisition of keys signals; 0 = serial, 1 = parallel. SYNC: selects the trigger type when SYNC Pin is selected as the trigger to start key acquisition. 0 = Level Acquisition starts when a "0" is read at the SYNC pin. If the pin is held low, the QT1110 operates in "Free run" mode (that is, it will not sleep in between acquisitions, but start again immediately). Acquisition starts when a rising edge is detected at the SYNC pin. When acquisition and post-processing are completed, the device sleeps until another rising edge is detected at the SYNC pin.
1 = Edge
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REPEAT_TIME: selects the "repeat" time when "Timed" is selected as the trigger to start key acquisition. The number entered is a multiple of 16 ms. If "0" is entered, the device will operate in a continuous "free run" mode; that is, the QT1110 will not sleep after its cycle is completed but will begin the next key acquisition cycle immediately. Default KEY_AC value: Default MODE value: Default SIGNAL value: Default SYNC value: Default REPEAT_TIME value: 1 (timed) 0 (7-key mode) 1 (parallel) 1 (edge) 2 (32 ms cycle)
7.5
Address 1: Guard Key/Comms Options
Table 7-3.
Address 1
Guard Key/Comms Options
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 GD_EN Bit 2 SPI_EN Bit 1 CHG Bit 0 CRC GUARD_KEY
GUARD_KEY: specifies the key (0 to 10) to be used as a guard channel (see Section 2.3 on page 7) . GD_EN: enables the use of a guard key; 0 = disable, 1 = enable. SPI_EN: enables the Quick SPI interface; 0 = disable, 1 = enable (see Table 7-4). Table 7-4.
Byte 0 1 2 3 4 5 6 Key 3 status Key 7 status Reserved Key 3 error Key 7 error Reserved Key 2 status Key 6 status Key 10 status Key 2 error Key 6 error Key 10 error
Status Information Bytes
Bit 7 Bit 6 Bit 5 Bit 4 Counter Key 1 status Key 5 status Key 9 status Key 1 error Key 5 error Key 9 error Key 0 status Key 4 status Key 8 status Key 0 error Key 4 error Key 8 error Bit 3 Bit 2 Bit 1 Bit 0
See Section 4.1.6 on page 16 for details of the Quick SPI Mode report. To exit this mode (and clear the "SPI_EN" bit), the command "0x36" should be sent. To save the settings to EEPROM and make Quick SPI mode active on startup, send the "Store to EEPROM" command (0x0A). Any other data sent is ignored in Quick SPI mode. CHG: the CHANGE pin mode (see Section 4.5 on page 17): 0 = "Data" mode. In this mode the "Change" pin is asserted to indicate unread data. 1 = "Touch" mode. In this mode the "Change" pin is asserted when a key is being touched or is in detect. CRC: enables or disables CRC; 0 = disable, 1 = enable. When this option is enabled, each data exchange must have a CRC byte appended. When report or setup data is being returned by the QT1110, a 1-byte checksum is returned. The host should confirm that this checksum is correct and, if not, should request the report again.
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Where data is being sent by the host, a 1-byte CRC should be sent. The QT1110 returns the expected CRC byte in the same transaction the CRC byte is sent. In this way, the host can immediately determine whether the setup data bytes were received correctly. Default GUARD_KEY value: Default GD_EN value: Default CHG value: Default CRC value: 0 (Key 0) 0 (disabled) 0 (data mode) 0 (disabled)
7.6
Address 2: Detect Integrator Limit (DIL)/Drift Hold Time (DHT)
Table 7-5.
Address 2
Detect Integrator/Drift Hold Time
Bit 7 Bit 6 DIL Bit 5 Bit 4 Bit 3 Bit 2 DHT Bit 1 Bit 0
DIL: the detection integrator (DI) limit. To suppress false detections caused by spurious events like electrical noise, the device incorporates a DI counter mechanism. A per-key counter is incremented each time the channel has exceeded its threshold and stayed there for a number of acquisitions in succession, without going below the threshold level. When this counter reaches a preset limit the channel is finally declared to be touched. If on any acquisition the delta is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. Note: A setting of 0 for DI is invalid; the valid range is 1 to 15. DHT: the drift hold time. After a key-touch has been removed, the QT1110 pauses in the implementation of its "Drift" compensation for a time. After this time has expired, drift compensation continues as normal. The "Drift Hold Time" is a multiple of 160 ms, providing options from 0 to 2400 ms. Default DIL value: Default DHT value: 3 8 (1280 ms)
7.7
Address 3: Positive Threshold (PTHR)/Positive Hysteresis (PHYST)
Table 7-6.
Address 3
Positive Threshold (THR)/Positive Hystereis (HYST)
Bit 7 Bit 6 Bit 5 PTHR Bit 4 Bit 3 Bit 2 Bit 1 PHYST Bit 0
PTHR: the positive threshold for the signal. If a key signal is significantly higher than the reference signal, this typically indicates that the calibration data is no longer valid. In other words, some factor has changed since the calibration was carried out, thus rendering it invalid. Generally this is compensated for by the drift, but the greater the difference the longer this will take. In order to speed up this correction, the positive threshold is used: if the positive threshold is exceeded, the QT1110 (that is, all keys) is recalibrated.
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PHYST: positive hysteresis. This setting provides a greater degree of control over the implementation of the positive threshold recalibration. The positive hysteresis operates as a "modifier" for the positive threshold. When a key signal is detected as being over the positive threshold, the positive threshold is reduced by a factor corresponding to the positive hysteresis so that the key will not go in and out of positive detection when the signal is on the borderline between drift-compensation of a positive error or recalibration. The settings for positive hysteresis are: 00 = No change to positive threshold 01 = 12.5 percent reduction in positive-detect threshold 10 = 25% reduction in positive-detect threshold 11 = 37.5% reduction in positive-detect threshold Default PTHR value: Default PHYST value: 4 (4 counts above reference) 2 (25% positive hysteresis)
7.8
Address 4: Positive Drift Compensation (PDRIFT)
Table 7-7.
Address 4
Positive Drift Compensation
Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 PDRIFT Bit 2 Bit 1 Bit 0
When changing ambient conditions cause a change in the key signal, the QT1110 will compensate through its drift functions. "Positive Drift" refers to the case where the signal for a key is greater than the reference. Drift compensation occurs at a rate of 1 count per drift compensation period. PDRIFT: the drift compensation period, in multiples of 160 ms. The valid range is 0 to 127, where 0 disables positive drift compensation. Note: Drift compensation timing is paused while Drift Hold is activated, and continued when Drift Hold has timed out. 6 (960 ms)
Default value:
7.9
Address 5: Positive Recalibration Delay (PRD)
Table 7-8.
Address 5
Positive Recalibration Delay
Bit 7 Bit 6 Bit 5 Bit 4 PRD Bit 3 Bit 2 Bit 1 Bit 0
If a key signal is determined to be above the positive threshold, the QT1110 will wait for this delay and confirm that the error condition is still present before initiating a recalibration. PRD: the positive recalibration delay, in multiples of 160 ms. Note: All keys are recalibrated in the case of a positive recalibration. 6 (960 ms) Default value:
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7.10 Address 6: Lower Burst Limit (LBL)
Table 7-9.
Address 6
Lower Burst Limit
Bit 7 Bit 6 Bit 5 Bit 4 LBL Bit 3 Bit 2 Bit 1 Bit 0
Normal QTouch signals are in the range of 100 to 1000 counts for each key. The lower burst limit determines the minimum signal that is considered as a valid acquisition. If the count is lower than the lower burst limit, it is considered not to be valid and the key is set to an Error state. Note: Where a key has a signal of less than the LBL, a detection is not reported on that key. 18 Default value:
7.11
Addresses 7-8: AKS Mask
Table 7-10.
Address 7 8 AKS_7 AKS_6 AKS_5 AKS_4 AKS_3
AKS Mask
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 AKS_10 AKS_2 Bit 1 AKS_9 AKS_1 Bit 0 AKS_8 AKS_0
AKS_n (AKS Mask): 0 = key n AKS disabled, 1 = key n AKS enabled (where n is 0-10). These bits control which keys have AKS enabled (see Section 3 on page 8). A "1" means the corresponding key has AKS enabled; a "0" means that the corresponding key has AKS disabled. Default AKS mask: 0x07 and 0xFF (all keys have AKS enabled)
7.12
Addresses 9-15: Detect0 - Detect6 PWM
Each of the 7 detect pins can be configured to output a PWM signal to indicate whether the key is touched (in detect) or not touched (out of detect). The Detect outputs must be enabled by selecting 7-key mode in the "Device Mode" setting (see Section 7.4 on page 29), and the corresponding "Key to LED" bits must be set to enable the individual "Detect" outputs for each key (see Section 7.14 on page 35). Table 7-11.
Address 9 10 11 12 13 14 15
Detect0 - Detect6 PWM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IN_DETECT0 IN_DETECT1 IN_DETECT2 IN_DETECT3 IN_DETECT4 IN_DETECT5 IN_DETECT6 OUT_DETECT0 OUT_DETECT1 OUT_DETECT2 OUT_DETECT3 OUT_DETECT4 OUT_DETECT5 OUT_DETECT6
IN_DETECTn: PWM to output when key n is "In Detect" (where n is 0-7).
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9520I-AT42-03/10
OUT_DETECTn: PWM to output when key n is "Out of Detect" (where n is 0-7). This PWM is also output if the DETECT output is "disconnected" from the key (that is, "LED_n" in address 17 is set to 0), allowing the host to directly control the PWM output. The values for the "IN_DETECTn" and "OUT_DETECTn" nibbles are listed in Table 7-12. Table 7-12.
Value 0 1 2 3 4 5 6 7 8
PWM Values
Meaning 0% 12.5% 25% 37.5% 50% 62.5% 75% 87.5% 100%
Default IN_DETECTn value: Default OUT_DETECTn value:
8 (100% PWM - on) 0 (0% PWM - off)
7.13
Address 16: LED Detect Hold Time
Table 7-13.
Address 16
LED Detect Hold Time
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LED_DETECT_HOLD_TIME
When a key is touched, if the "Detect" outputs and "Key to LED" options are enabled (see Section 7.12 and Section 7.14), the corresponding "Detect" pin will output its "In-Detect" PWM signal. After the key touch is removed, the "Detect" output can be held at the "In-Detect" PWM signal for a time before returning to the "Out of Detect" PWM signal. This allows a reasonable length of time for an LED to be illuminated. The length of this time is controlled by the LED Detect Hold Time. Valid values are in multiples of 16 ms. Default value: 0 (0 ms)
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7.14 Address 17: LED Fade/Key to LED
Table 7-14.
Address 17
LED Fade/Key to LED
Bit 7 FADE Bit 6 LED_6 Bit 5 LED_5 Bit 4 LED_4 Bit 3 LED_3 Bit 2 LED_2 Bit 1 LED_1 Bit 0 LED_0
FADE: enables/disables fading for all LEDs. This is a global setting; either all LEDs fade, or none of them. 0 = disable (no fade). 1 = enable fading on and off. LED_n: activates the LED output for the corresponding key output DETECTn (where n is 0-6). 1 = enables the "Detect" output to follow the status of the corresponding key. 0 = disable this function, in which case the "Detect" pin will always output its "Out of Detect" PWM (see Section 7.12 on page 33). Default FADE value: Default LED_n value: 0 (disabled) 1 (enabled)
7.15
Address 18: LED Latch
Table 7-15.
Address 18
LED Latch
Bit 7 0 Bit 6 LATCH_6 Bit 5 LATCH_5 Bit 4 LATCH_4 Bit 3 LATCH_3 Bit 2 LATCH_2 Bit 1 LATCH_1 Bit 0 LATCH_0
LATCH_n: enables/disables latching of the LED for the corresponding key output DETECTn (where n is 0-6). 1 = enables latching. When latching is enabled for a given LED, the LED toggles its state each time the key is touched. 0 = disables latching. Note that bit 7 is reserved and should be set to zero. Default LATCH_n value: 0x00 (latch disabled)
7.16
Addresses 19-29: Negative Threshold (NTHR)/Negative Hysteresis (NHYST)
Table 7-16.
Address 19 20 21 22 23 24
Negative Threshold/Negative Hysteresis
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KEY_0_NTHR KEY_1_NTHR KEY_2_NTHR KEY_3_NTHR KEY_4_NTHR KEY_5_NTHR KEY_0_NHSYT KEY_1_NHSYT KEY_2_NHSYT KEY_3_NHSYT KEY_4_NHSYT KEY_5_NHSYT
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Table 7-16.
Address 25 26 27 28 29
Negative Threshold/Negative Hysteresis (Continued)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KEY_6_NTHR KEY_7_NTHR KEY_8_NTHR KEY_9_NTHR KEY_10_NTHR KEY_6_NHSYT KEY_7_NHSYT KEY_8_NHSYT KEY_9_NHSYT KEY_10_NHSYT
KEY_n_NTHR: the negative threshold for key n (where n is 0-10). The negative threshold determines how much the signal must fall (compared to the reference) before a key is considered to be "In Detect". This level will generally need to be tuned individually for each key. To disable an individual key, set the threshold for that key to 0. KEY_n_NHYST: the negative hysteresis applied to key n detection threshold (where n is 0 - 10). Negative Hysteresis operates as a "modifier" for the negative threshold in order to provide a greater degree of control over the detection of a "Touch". When a key signal is first detected as being under the negative threshold, the threshold is reduced by a factor corresponding to the selected negative hysteresis. This means that the key will not go in and out of detection when the signal is on the borderline between drift-compensation or touch detection. The settings for negative hysteresis are: 00 01 10 11 No change to negative threshold 12.5% reduction in negative threshold 25% reduction in negative threshold 37.5% reduction in negative threshold 10 counts 2 (25 percent)
Default KEY_n_NTHR value: Default KEY_n_NHYST value:
7.17
Address 30: Extend Pulse Time
Table 7-17.
Address 30
Extend Pulse Time
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HIGH_TIME
LOW_TIME
HIGH_TIME: Number of s to extend the high pulse time. LOW_TIME: Number of s to extend the low pulse time.
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7.18 Addresses 31-41: Negative Drift Compensation (NDRIFT)/Negative Recalibration Delay (NRD)
Table 7-18.
Address 31 32 33 34 35 36 37 38 39 40 41
Negative Drift Compensation/Negative Recalibration Delay
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KEY_0_NDRIFT KEY_1_NDRIFT KEY_2_NDRIFT KEY_3_NDRIFT KEY_4_NDRIFT KEY_5_NDRIFT KEY_6_NDRIFT KEY_7_NDRIFT KEY_8_NDRIFT KEY_9_NDRIFT KEY_10_NDRIFT KEY_0_NRD KEY_1_NRD KEY_2_NRD KEY_3_NRD KEY_4_NRD KEY_5_NRD KEY_6_NRD KEY_7_NRD KEY_8_NRD KEY_9_NRD KEY_10_NRD
KEY_n_NDRIFT: the negative drift compensation for key n (where n is 0-10). When changing ambient conditions cause a change in the key signal, the QT1110 will compensate through its drift functions. "Negative Drift" refers to the case where the signal for a key is lower than the reference. Drift compensation occurs at a rate of 1 count per drift compensation period. The entered number is a multiple of 320 ms. Note that as a key touch, or an approaching touch, naturally causes a negative change in the signal, negative drift should be carried out at a much slower rate than positive drift. Otherwise, a slowly approaching finger will not cause a touch detection, as the falling signal could be compensated through the negative drift mechanism. Note: Drift compensation timing is paused while Drift Hold is activated, and continues when Drift Hold has timed out.
KEY_n_NRD: the negative recalibration delay for key n (where n is 0-10). In order to avoid a situation where a key remains "stuck" in detect due to, for example, changing environmental conditions, the "Negative Recalibration Delay" sets an upper limit on how long a key can remain "touched". When this time is exceeded, the QT1110 (that is, all keys) is recalibrated, taking this key (and any others which are in detect) out of detection. This delay is set in a multiple of 2560 ms. Note: A setting of "0" disables the NRD Timeout. 7 (2240 ms) 10 (25.6 seconds) Default KEY_n_NDRIFT value: Default KEY_n_NRD value:
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8. Specifications
8.1
Vdd Max continuous pin current, any control or drive pin Voltage forced onto any pin EEPROM setups maximum writes
Absolute Maximum Specifications
-0.5 to +6V 10 mA -1.0V to (Vdd + 0.5) Volts 100,000 write cycles
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification conditions for extended periods may affect device reliability
8.2
Recommended Operating Conditions
-40C to +85C -65C to +150C 3V to 5.5V 20 mV 2 to 20 pF
Operating temperature Storage temperature Vdd Supply ripple + noise Cx transverse load capacitance per key
8.3
DC Specifications
Vdd = 5.0V, Cs = 4.7 nF, Rs = 1 M, Ta = recommended range, unless otherwise noted
Parameter Iddr Vil Vih Vol Voh Iil Rrst Description Average supply current, running Low input logic level High input logic level Low output voltage High output voltage Input leakage current Internal RST pull-up resistor Min - -0.5V 0.6 Vdd 0 0.8 Vdd - 30 Typ - - Vdd - - <0.05 - Max 12 at 5V 8 at 3V 0.3 Vdd Vdd + 0.5V 0.7 Vdd 1 60 Units mA V V V V A k 10 mA sink current 10 mA source current Notes For typical values see Section 8.8
8.4
Timing Specifications
Description Burst duration Burst center frequency Burst modulation, percentage Pulse width Min - - - - Typ 5 53 18 6000 Max - - - - Units ms kHz % ns Notes 4.7 nF Cs
Parameter TBS Fc Fm TPW
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8.5
8.5.1
Parameter Address space Maximum clock rate Minimum low clock period Minimum high clock period Clock idle Setup on Clock out on SPI Enable delay (SS low to SCK low)
SPI Bus Specifications
General Specifications
Specification 8-bit 1.5 MHz 333 ns 333 ns High Leading (falling) edge Trailing (rising) edge 1 s
8.5.2
Parameter
Full SPI Mode
Specification 150 s Generally 150 s; longer delays required to implement some commands, as follows: * Send Setups: 150 s after all setup bytes are returned * Calibrate All: 150 s * Calibrate Key: 150 s * Reset: 160 ms * Sleep: 150 s after a low signal is applied to SS or CHANGE to wake the device * Store to EEPROM: 200 ms * Restore from EEPROM: 150 ms * Erase EEPROM: 50 ms * Recover EEPROM: 50 ms
Time between bytes
Time between communications
8.5.3
Parameter
Quick SPI Mode
Specification 50 s Generally 50 s, except for the following:
Time between bytes
Time between communications
* Store to EEPROM: 200 ms * Switch to Full SPI: 150 s
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9520I-AT42-03/10
Figure 8-1.
Signals on SPI Pins During the Exchange of a Data Byte
SCK
SAMPLE MOSI/MISO CHANGE MOSI PIN CHANGE MISO PIN SS
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
8.6
External Reset
Description Threshold voltage low (Activate) Threshold voltage high (Release) Minimum length of Reset low Operation 0.2Vdd 0.9Vdd 600 ns at 5V 1100 ns at 3V
Parameter VRST Reset
8.7
Internal Resonator
Operation 8 MHz with spread-spectrum modifier during measurement bursts
Parameter Internal RC oscillator
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8.8
9520I-AT42-03/10
4.7 nF Cs Capacitors
7-key Parallel Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) 13.2 ms 17.2 ms 33.6 ms 66.4 ms 132 ms 248 ms 15.1 ms 17.2 ms 33.4 ms 65.6 ms 130 ms 244 ms 2440 244 ms 3035 246 ms 2465 245 ms 2705 132 ms 3225 130 ms 2840 132 ms 3120 66.8 ms 4015 65.6 ms 3240 67.6 ms 4210 34.4 ms 5350 33.6 ms 4013 43.6 ms 5290 30.2 ms 5405 17.3 ms 5674 43.6 ms 5425 5425 4130 3530 3015 5530 30.2 ms 5405 17.3 ms 5674 43.6 ms 5425 815 250 ms 850 250 ms 810 250 ms 1008 840 133 ms 1025 132 ms 840 134 ms 1120 1010 67.2 ms 1325 66.4 ms 1045 68.4 ms 1587 66 ms 132 ms 248 ms 2.15 ms 16.3 ms 32.6 ms 64.8 ms 129 ms 244 ms 1470 34.4 ms 1950 33.8 ms 1435 37.4 ms 2420 33 ms 2180 26.6 ms 2350 17.3 ms 2182 37.4 ms 2420 16.5 ms 2470 26.6 ms 2350 15.3 ms 2385 37.4 ms 2420 2.15 ms 2107 950 739 691 668 656 4860 2965 2400 2248 2206 2163 7-key Serial 11-key Parallel 11-key Serial 11-key Serial, 1 key enabled
Vdd (V)
Cycle Time
0 (Free Run)
1 (16 ms Nominal)
3.0V
2 (32 ms Nominal)
4 (64 ms Nominal)
Power Consumption
8 (128 ms Nominal)
15 (240 ms Nominal)
0 (Free Run)
1 (16 ms Nominal)
5.0V
2 (32 ms Nominal)
4 (64 ms Nominal)
8 (128 ms Nominal)
15 (240 ms Nominal)
Note:
These values are for reference only; values are untested.
10 nF Cs Capacitors
7-key Parallel 7-key Serial 11-key Parallel 11-key Serial 11-key Serial, 1 key enabled Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) Actual Cycle Time Idd (A) 24.2 ms 24.2 ms 34.4 ms 66.8 ms 131 ms 246 ms 26 ms 26 ms 34 ms 66 ms 131 ms 244 ms 2950 3290 3990 5170 5810 56.4 ms 56.4 ms 67.6 ms 132 ms 244 ms 5810 56.4 ms 845 248 ms 995 133 ms 1320 1030 5510 5510 5510 5120 3850 3310 1285 68.4 ms 1910 1860 48.4 ms 2430 2375 48.4 ms 2430 2375 48.4 ms 2430 24.2 ms 24.2 ms 34 ms 66.4 ms 132 ms 246 ms 28 ms 28 ms 34 ms 66.4 ms 130 ms 242 ms 2434 2434 1945 1290 980 824 5675 5675 5196 3780 2910 2675 63.6 ms 63.6 ms 63.6 ms 69.6 ms 134 ms 248 ms 73.6 ms 73.6 ms 73.6 ms 73.6 ms 133 ms 246 ms 2416 2416 2416 2260 1485 1080 5596 5596 5596 5596 4055 3170 8.6 ms 16.7 ms 33 ms 65 ms 130 ms 243 ms 8.6 ms 16.6 ms 32.6 ms 64.8 ms 129 ms 241 ms 2130 1422 1065 848 766 708 5145 3990 3160 2690 2310 2270
Vdd (V)
Cycle Time
0 (Free Run)
1 (16 ms Nominal)
3.0V
2 (32 ms Nominal)
4 (64 ms Nominal)
8 (128 ms Nominal)
15 (240 ms Nominal)
0 (Free Run)
1 (16 ms Nominal)
5.0V
2 (32 ms Nominal)
4 (64 ms Nominal)
8 (128 ms Nominal)
15 (240 ms Nominal)
Note:
These values are for reference only; values are untested.
AT42QT1110-MU/AT42QT1110-AU
41
8.9
8.9.1
Mechanical Dimensions
AT42QT1110-MU - 32-pin 5 x 5 mm MLF
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1
K
P D2
A
0.08 C
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 BSC 0.30 - - 0.20 - 0.40 - - 0.50 0.60 12o - 0.30 5.10 4.80 3.25 5.10 4.80 3.25 MAX 1.00 0.05 1.00 NOTE
SYMBOL A
P
Pin #1 Notch (0.20 R)
1 2 3
A1 A2 A3 E2 b
K
D D1 D2 E
b
e
L
E1 E2 e L P
BOTTOM VIEW
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. E
R
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8.9.2 AT42QT1110-AU - 32-pin 7 x 7 mm TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B
R
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9520I-AT42-03/10
8.10
8.10.1
Marking
AT42QT1110-MU - 32-pin 5 x 5 mm MLF Either of the following markings may be used.
Pin 1 ID
32
Abbreviation of Part Number: AT42QT1110-MU
1
1110 4R5
Code revision: 4.5 Released
Program week code number 1-52 where: A = 1, B = 2...Z = 26 then using the underscore A = 27...Z = 52
Pin 1 ID
32
1
Abbreviation of Part Number: AT42QT1110-MU
Datecode/ Lot Number
ATMEL QT1110 MU 4R5 Date code Country Code
Lot number
Code Revision: 4.5, Released
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8.10.2 AT42QT1110-AU - 32-pin 7 x 7 mm TQFP Either of the following markings may be used.
32 Pin 1 ID
1
Abbreviation of Part Number: AT42QT1110-AU
QT1110 AU 4R5
Code Revision: 4.5, Released Program week code number 1 where: A = 1, B = 2...Z = 26 then using the underscore A = 27...Z = 52
32 Pin 1 ID
1 Abbreviation of Part Number: AT42QT1110-AU
Datecode/ Lot Number
ATMEL QT1110 AU 4R5 DATE/LOT
Code Revision: 4.5, Released
8.11
Part Number
Part Number AT42QT1110-MU AT42QT1110-AU Description 32-pin 5 x 5 mm MLF RoHS compliant (-40C to +85C) 32-pin 7 x 7 mm TQFP RoHS compliant (-40C to +85C)
8.12
Moisture Sensitivity Level (MSL)
MSL Rating MSL3 Peak Body Temperature 260oC Specifications IPC/JEDEC J-STD-020
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Appendix A.
CRC Calculation
If the use of a cyclic redundancy check (CRC) during data transmission is enabled, the host must generate a valid CRC so that this can be correctly compared to the corresponding CRC generated by the QT1110. This appendix gives example C code to show how the CRC can be generated by the host.
/*======================================================================= unsigned char calc_crc(unsigned char crc, unsigned char data) --------------------------------------------------------------------------Purpose: Calculate CRC for data packets Input : CRC, Data Output : Updated CRC Notes : =========================================================================*/ unsigned char calc_crc(unsigned char crc, unsigned char data) { unsigned char index; unsigned char fb; index = 8; do { fb = (crc ^ data) & 0x01u; data >>= 1u; crc >>= 1u; if(fb) { crc ^= 0x8c; } } while(--index); return crc; } /* Example Calling Routine */ unsigned char calculate_config_checksum(void) { int i; unsigned char CRC_val = 0; unsigned char setup_data[42] = { 0xB2, 0x00, 0x38, 0x12, 0x06, 0x06, 0x12, 0x07, 0xFF, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x32, 0xFF, 0x00, 0x29, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0X00, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A }; for(i = 0; i < sizeof(setup_data); i++) { CRC_val = calc_crc(CRC_val, setup_data[i]); } return(CRC_val); }
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Revision History
Revision No. Revision A - November 2008 Revision B - December 2008 Revision C - December 2008 Revision D - February 2009 Revision E - April 2009 Revision F - July 2009 Revision G - October 2009 Revision H - February 2010 Revision I - March 2010 History Initial Release Updated for chip revision 2.1 Updated SPI specifications Updated for chip revision 3.1 Updated for chip revision 3.2: added self-test function Updated for chip revision 4.3: added Quick SPI mode Updated for chip revision 4.4 Updated specifications Description of Quick SPI mode timing updated Updated for chip revision 4.5
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
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Product Contact
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Literature Requests
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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9520I-AT42-03/10

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